CXMT says G5 DRAM platform is in mass production

ChangXin Memory Technologies (CXMT) said its fifth-generation DRAM manufacturing platform has entered mass production and showed two 24-gigabit LPDDR5X chips already in volume production for smartphones and other portable devices.

HARDWARE desk — Memory chips sit under every AI and phone workload. A Chinese DRAM supplier claiming a denser, higher-die-count mass-production node matters because the global market is still dominated by Samsung, SK Hynix, and Micron — so any credible extra source of advanced DRAM changes how buyers and governments think about supply risk, even when the first chips are phone memory rather than AI HBM.

The company unveiled two 24-gigabit LPDDR5X products made on G5 — a 496-ball package and a 245-ball package — and said both are already in volume production for smartphones and other portable electronics. LPDDR5X is a lower-power kind of DRAM used mainly in phones and other portable devices. File those two products, the two packages, and the already-in-volume-production line as CXMT’s, via Reuters, China Daily, and Global Times. This desk did not open a phone or count a shipment.

CXMT said each 24Gb product holds 50% more data than its previous equivalent products. File that 50% density step as CXMT’s versus its own last comparable chips. This desk did not measure a die.

CXMT said G5 uses quadruple patterning to shrink the active-area half-pitch in the memory array to 11.95 nanometers. Half-pitch here is a spacing measurement inside the memory array — how close the data-storing features sit — not a logic-chip “node name” like the 2nm label on a phone processor. Luo Xiaodong said process capability is “on par with the most advanced mass-produced nodes” in the industry. File the 11.95-nanometer half-pitch, the quadruple-patterning method, and that on-par line as CXMT’s / Luo’s. “On par” is his wording — not a desk ranking versus Samsung, SK Hynix, or Micron. This desk did not meter a wafer.

CXMT said the platform can produce at least 50% more gross dies per wafer than its fourth-generation platform, using an 8-gigabit-chip baseline before defect screening. A die is one chip cut from a silicon wafer. Gross dies means the potential number of chips on the wafer before broken units are thrown out — a die-count claim, not a final yield claim, and not a promise that 50% more good chips ship. File that ≥50% gross-die line as CXMT’s. This desk did not count dies or audit yield.

DRAM — dynamic random-access memory — is the short-term working memory phones, computers, and other devices use to run apps and programs. This filing is about CXMT’s mobile and portable LPDDR5X products. Do not read this card as CXMT shipping HBM — high-bandwidth memory stacked for AI accelerators. No source in this pack says that.

Context only, do not overclaim: the advance lands as China seeks more domestic semiconductor supply, and U.S. export controls since 2022 have limited access to some advanced chipmaking tools. File that backdrop as Reuters’ same-day framing — not as a license outcome this desk verified, and not as a claim CXMT now matches the three global DRAM incumbents on every product.

Plain English for the rest of the card: DRAM = short-term working memory. LPDDR5X = a lower-power DRAM used mainly in phones and portable devices. G5 = CXMT’s fifth-generation manufacturing platform. die = one chip cut from a wafer. wafer = the round silicon disc chips are printed on. gross dies = chips counted before defect screening — not final yield. quadruple patterning = repeating process steps to print finer features. half-pitch = spacing of features in the memory array. 24Gb = 24 gigabits of data on one chip. HBM = high-bandwidth memory for AI accelerators — not what this card is filing. 688825.SS = CXMT’s STAR Market ticker. Luo Xiaodong = CXMT vice president, named at the Hefei convention.

CONFIRMED here: Reuters’ 20 Sep 2026 Beijing report of CXMT’s G5 mass-production claim at the World Manufacturing Convention — Tier B, not a CXMT newsroom PRIMARY. China Daily and Global Times are same-day independent corroboration of the company remarks, the 24Gb LPDDR5X products, the 496-ball / 245-ball packages, the 50% density step, the 11.95-nanometer half-pitch, and the ≥50% gross-die line — not a substitute primary. The G5 mass-production claim, the two 24Gb LPDDR5X products already in volume production, the 50% more-data line, the quadruple-patterning / 11.95-nanometer half-pitch picture, Luo’s on-par quote, and the ≥50% gross-die / 8-gigabit-baseline / before-defect-screening line are CXMT-attributed via those papers. NOT claimed: HBM for AI accelerators, an independently measured yield, a named phone model this desk verified, that CXMT now matches Samsung / SK Hynix / Micron on every DRAM product, a U.S. export-license outcome, that this desk sat in the hall or walked a fab, a stock tip, or investment advice. Distinct from the already-filed huawei-ascend-960-supernode, mediatek-dimensity-9600-pro, nubia-navix-ultra-ga, and nvidia-vera-rubin-nvl72-mlperf.