Synopsys and TSMC deepen AI chip-design stack with agentic EDA on A14

Synopsys announced new collaborations with TSMC spanning A14 design enablement with agentic AI capabilities, AI-assisted analog, digital, and multi-die workflows, CoWoS support for integrated voltage regulators, and joint enablement for TSMC-COUPE co-packaged optics.

HARDWARE desk — the companies that draw the blueprints for AI chips are putting agentic AI inside the design tools themselves, so the next AI accelerators get built with AI copilots on A14 and advanced packaging.

What the release says the work is for. The subhead says the new collaborations span A14 design enablement, AI-assisted engineering workflows, CoWoS support for multi-die designs, and unified multiphysics signoff. The bullets say certified EDA flows on TSMC A14 speed design readiness for AI and high-performance computing. EDA is electronic design automation, the software that designs chips. A14 is the advanced TSMC process node named in the release. The page does not print a transistor width next to that name. Recent achievements, the release says, include A14 certification across digital and analog flows, and enablement of agentic AI capabilities. The certified flows are a methodology that spans implementation through signoff, meant to speed design convergence on A14. Implementation is laying the chip out. Signoff is the last check that the design meets the rules before a factory makes it. Design convergence means the design stops moving and is ready. These lines are the release’s. This desk did not certify a flow.

The analog step, in the release’s tense. In analog design, Synopsys is collaborating with TSMC to achieve device routing enablement on A14. The release calls that a key milestone for advanced analog place-and-route automation that boosts layout productivity and speeds adoption of the new process. Analog, here, means circuits that handle continuous signals, such as power and radio, not only on-or-off logic. Place-and-route is the software that decides where the pieces sit and how the wires run. Device routing is that wiring step for analog parts. “To achieve” is the release’s verb. It is a collaboration milestone, not a sentence that says every analog block is already certified. These lines are the release’s.

The agentic workflows, and what that word means on this card. Synopsys, with TSMC, says it is using agentic AI to automate analog, digital, and multi-die design so the work is more productive and more autonomous. Agentic AI, here, means software that runs a multi-step design job. It is not a chatbot that answers one question. Custom Compiler accelerates analog migration, which means moving an existing analog design onto a newer process. Fusion Compiler uses LLM-assisted analysis to boost productivity. An LLM is a large language model, the kind of model that reads and writes text. For multi-die designs, a new agentic AI chiplet floorplan co-optimization flow on the 3DIC Compiler platform automates floorplanning and supports TSMC 3DFabric. A chiplet is a small chip meant to sit beside other chips in one package. A floorplan is the map of where those pieces go. Multi-die means more than one chip in that package. 3DFabric is TSMC’s name for its advanced packaging family. These product names and claims are the release’s. This desk did not open the tools.

Power, still the release. As AI systems need more electricity delivered cleanly, integrated voltage regulators, shortened to IVRs, are a way to improve power efficiency and power integrity in multi-die designs. A voltage regulator keeps the electricity at the level a chip needs. Integrated means that regulator is built into the package, not only on a board beside it. Power integrity means the electricity stays steady enough that the chip does not glitch. The release also names thermal requirements, which means heat. Synopsys 3DIC Compiler now lets designers co-design and simulate an IVR on TSMC CoWoS in one environment. CoWoS is TSMC’s advanced packaging for putting several dies on one interposer, the base that connects them. The release’s word is continued enablement. This is not a sentence that says IVR-on-CoWoS started today. These lines are the release’s.

Light, in the same release. Optical connections are becoming important for fast links between chips. Synopsys continues to work with TSMC on co-packaged optics, shortened to CPO, on TSMC COUPE. Co-packaged optics means the light-based connections sit in the same package as the electronic chips, instead of on a separate board. COUPE is TSMC’s name for that optics technology. The flow is an integrated photonic and electronic co-design that spans 3DIC implementation, multiphysics analysis, and optimization. Photonic means the part that uses light. Multiphysics means the check looks at more than one kind of physics at once, such as heat and electricity together. The release says both companies help customers develop and verify those optical links for multi-die systems. Continued, again, is the release’s word. This desk did not measure a light path.

The licensed blocks on N2P, as a list, not as a bench this desk ran. On TSMC’s N2P process, Synopsys says it reached IP enablement and tape-out milestones for AI and high-performance computing, including PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP, and SLM process, voltage, and temperature monitoring IP. N2P is a TSMC 2-nanometer process named in the release. IP, here, is a finished block of chip design a customer can license. Tape-out is handing a finished design to a factory. PCIe 7.0 is a very fast connection standard between a chip and the cards around it. HBM4 is a generation of high-bandwidth memory, the stacked memory used beside AI chips. LPDDR6, LPDDR5X, and LPDDR5 are low-power memory standards. A 224G Ethernet PHY is the physical circuit for Ethernet at 224 gigabits a second. UCIe is a standard for connecting dies inside one package. OTP is one-time programmable memory, a block you write once. SLM is Silicon Lifecycle Management, software and monitors that watch a chip after it is made. PVT is process, voltage, and temperature, the three things that monitor watches. The release says these blocks deliver high-bandwidth connectivity, memory performance, and real-time system intelligence. It also calls the wider set the industry’s broadest portfolio of silicon-proven interface, foundation, and SLM IP. Broadest is the company’s comparative. This desk did not count a rival’s catalog.

Three die-to-die sentences that do not collapse into one. Synopsys demonstrated UCIe-A silicon at 32G and 40G on a TSMC N3P test chip integrated with a CoWoS-S interposer. N3P is a TSMC 3-nanometer process. CoWoS-S is the CoWoS variant named in the release. 32G and 40G are 32 and 40 gigabits a second, the speeds the release prints. The release says that demo validates high-speed die-to-die connectivity for AI systems. A separate sentence says Synopsys recently completed 64G UCIe IP tape-outs on both 2nm and 3nm, and that the IP provides in-system visibility with embedded DFT. DFT is design for test, the hooks that let a factory test the chip. 64G is not 32G, and it is not 40G. A third sentence says Synopsys expanded silicon-proven Foundation, MIPI, and memory IP for N3P and N2P, and is developing IP on compact “C” process technologies from 6nm through 3nm. MIPI is a family of connection standards used in phones and cameras. “C” is the release’s name for those compact processes. Developing is not the same verb as demonstrated, and it is not the same verb as tape-out. The release also says the portfolio builds on first-silicon success across N5, N3P, and N2P. First silicon means a chip that has come back from the factory and works. These lines are the release’s.

The quotes, and only the release. Michael Buehler-Garcia, senior vice president at Synopsys, said customers need proven IP, intelligent design solutions, and advanced packaging methodologies that work together, and that the joint work with TSMC covers silicon-to-systems co-design for next-generation AI and high-performance computing. Aveek Sarkar, director of the Ecosystem and Alliance Management Division at TSMC, said the collaboration with Open Innovation Platform partners such as Synopsys meets the demand from AI and high-performance computing. Open Innovation Platform, shortened to OIP, is TSMC’s partner program. He said combining Synopsys certified EDA and silicon-proven IP with TSMC’s latest process and packaging lets customers push performance, integration, and energy efficiency. A quote is the speaker’s sentence. This desk did not interview them.

Plain English for the rest of the card. EDA is the software that designs chips. A14 is the TSMC process node in this release. Agentic AI, here, is a multi-step design workflow, not a chat box. Custom Compiler, Fusion Compiler, and 3DIC Compiler are Synopsys tools named for analog migration, text-model analysis, and multi-die floorplanning. A chiplet is a small chip in a multi-die package. CoWoS is TSMC packaging that sets several dies on one connecting base. An IVR is a voltage regulator built into that package. COUPE is TSMC’s co-packaged optics, light links in the same package as the chips. N2P is the 2-nanometer process. N3P is the 3-nanometer process. IP is a licensable design block. Tape-out is sending that block to be manufactured. PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet, UCIe, OTP, and PVT monitors are the N2P list. 32G/40G is the demonstrated UCIe-A silicon. 64G is the separate tape-out speed. OIP is TSMC’s partner program. 3:01 p.m. Eastern is the PR Newswire stamp. The newsroom page this desk read has the date and no hour.

PRIMARY here: Synopsys’s 23 Sep 2026 newsroom post — Tier A PRIMARY, the company’s own announcement. The page did not print an hour. PR Newswire’s syndication of the same release, stamped Sep 23, 2026, 15:01 ET, is the wire clock and the same text, not a second set of claims. The A14 certification across digital and analog flows, the agentic-AI enablement line, the implementation-through-signoff methodology, the device-routing collaboration, Custom Compiler analog migration, Fusion Compiler LLM-assisted analysis, the 3DIC Compiler chiplet floorplan flow on 3DFabric, IVR co-design and simulation on CoWoS, COUPE photonic and electronic co-design, the N2P list (PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY, UCIe, OTP, and SLM PVT monitoring IP), the UCIe-A 32G/40G demo on N3P with CoWoS-S, the 64G UCIe tape-outs on 2nm and 3nm, the Foundation, MIPI, and memory expansion, the compact “C” processes from 6nm through 3nm, the first-silicon line across N5, N3P, and N2P, the broadest-portfolio comparative, and the Buehler-Garcia and Sarkar quotes are the release’s. NOT claimed: a transistor width for A14, that device routing is already certified, that IVR-on-CoWoS or COUPE started today, that 32G, 40G, and 64G are one speed, that this desk ran a tool or counted a rival IP catalog, a customer win, a revenue figure, a stock tip, or investment advice. Distinct from the already-filed sprind-nadi-ai-chip-design, amazon-seller-assistant-agentic, and bessemer-5-75b-ai-funds.